Kinetis SDK v.1.3 API Reference Manual  Rev. 0
Freescale Semiconductor, Inc.
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Groups Pages
Macros | Enumerations
fsl_sim_hal_MKM34Z7.h File Reference
KM34Z7 SIM HAL driver
#include <assert.h>

Macros

#define FSL_SIM_SCGC_BIT(SCGCx, n)   (((SCGCx-1U)<<5U) + n)
 

Enumerations

enum  clock_wdog_src_t {
  kClockWdogSrcLpoClk,
  kClockWdogSrcOsc32kClk,
  kClockWdogSrcMcgIrClk,
  kClockWdogSrcEr32kClk,
  kClockWdogSrcLpoClk,
  kClockWdogSrcAltClk,
  kClockWdogSrcLpoClk,
  kClockWdogSrcAltClk,
  kClockWdogSrcLpoClk,
  kClockWdogSrcAltClk,
  kClockWdogSrcLpoClk,
  kClockWdogSrcAltClk,
  kClockWdogSrcLpoClk,
  kClockWdogSrcAltClk
}
 WDOG clock source select. More...
 
enum  clock_afe_src_t {
  kClockAfeSrcPllClk,
  kClockAfeSrcFllClk,
  kClockAfeSrcOscClk,
  kClockAfeSrcExt
}
 AFE clock source select. More...
 
enum  clock_lptmr_src_t {
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClk,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClk,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClk,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClk,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClk,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClkUndiv,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClkUndiv,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClkUndiv,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClkUndiv,
  kClockLptmrSrcMcgIrClk,
  kClockLptmrSrcLpoClk,
  kClockLptmrSrcEr32kClk,
  kClockLptmrSrcOsc0erClkUndiv
}
 LPTMR clock source select, table 5-2. More...
 
enum  clock_slcd_src_t {
  kClockSLcdSrcMcgIrClk,
  kClockSLcdSrcOsc32kClk
}
 LCD clock source select, table 5-2.
 
enum  clock_er32k_src_t {
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcReserved = 1U,
  kClockEr32kSrcRtc = 2U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcReserved = 1U,
  kClockEr32kSrcRtc = 2U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcReserved = 1U,
  kClockEr32kSrcRtc = 2U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcReserved = 1U,
  kClockEr32kSrcRtc = 2U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc32kClk = 0U,
  kClockEr32kSrcEr32kClk = 1U,
  kClockEr32kSrcMcgIrClk = 2U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcLpo = 3U,
  kClockEr32kSrcOsc0 = 0U,
  kClockEr32kSrcLpo = 3U
}
 SIM external reference clock source select (OSC32KSEL) More...
 
enum  clock_clkout_src_t {
  kClockClkoutReserved = 0U,
  kClockClkoutReserved1 = 1U,
  kClockClkoutBusClk = 2U,
  kClockClkoutLpoClk = 3U,
  kClockClkoutMcgIrClk = 4U,
  kClockClkoutReserved2 = 5U,
  kClockClkoutOsc0erClk = 6U,
  kClockClkoutReserved3 = 7U,
  kClockClkoutReserved = 0U,
  kClockClkoutReserved1 = 1U,
  kClockClkoutBusClk = 2U,
  kClockClkoutLpoClk = 3U,
  kClockClkoutMcgIrClk = 4U,
  kClockClkoutReserved2 = 5U,
  kClockClkoutOsc0erClk = 6U,
  kClockClkoutReserved3 = 7U,
  kClockClkoutReserved = 0U,
  kClockClkoutReserved1 = 1U,
  kClockClkoutBusClk = 2U,
  kClockClkoutLpoClk = 3U,
  kClockClkoutMcgIrClk = 4U,
  kClockClkoutReserved2 = 5U,
  kClockClkoutOsc0erClk = 6U,
  kClockClkoutReserved3 = 7U,
  kClockClkoutReserved = 0U,
  kClockClkoutReserved1 = 1U,
  kClockClkoutBusClk = 2U,
  kClockClkoutLpoClk = 3U,
  kClockClkoutMcgIrClk = 4U,
  kClockClkoutReserved2 = 5U,
  kClockClkoutOsc0erClk = 6U,
  kClockClkoutReserved3 = 7U,
  kClockClkoutGatedCoreClk = 1U,
  kClockClkoutBusFlashClk = 2U,
  kClockClkoutLpoClk = 3U,
  kClockClkoutMcgIrClk = 4U,
  kClockClkoutOsc32kSel = 5U,
  kClockClkoutOsc0erClk = 6U,
  kClockClkoutMcgPllClk = 7U
}
 SIM CLKOUT_SEL clock source select.
 
enum  clock_rtcout_src_t {
  kClockRtcoutSrc1Hz,
  kClockRtcoutSrc32kHz,
  kClockRtcoutSrc1Hz,
  kClockRtcoutSrc32kHz,
  kClockRtcoutSrc1Hz,
  kClockRtcoutSrc32kHz,
  kClockRtcoutSrc1Hz,
  kClockRtcoutSrc32kHz,
  kClockRtcSrcRtcOsc32kClk,
  kClockRtcSrcMcgIrClk
}
 SIM RTCCLKSEL clock source select, SIM_MISC_CTL.
 
enum  clock_lpuart_src_t {
  kClockLpuartSrcNone,
  kClockLpuartSrcPllFllSel,
  kClockLpuartSrcOsc0erClk,
  kClockLpuartSrcMcgIrClk
}
 SIM LPUART clock source selection, SIM_CTRL_REG.
 
enum  sim_tmr_cnt_freeze_sel_t {
  kSimTmrCntFreezeEnable,
  kSimTmrCntFreezeDisable
}
 SIM TMR counter freeze control, SIM_CTRL_REG.
 
enum  sim_afe_clk_div_sel_t {
  kSimAfeClkDivEnable,
  kSimAfeClkDivDisable
}
 SIM AFE clock out dividing setting, SIM_CTRL_REG.
 
enum  clock_xbar_out_src_t {
  kClockXbarOutGatedCoreClk = 1U,
  kClockXbarOutBusFlashClk = 2U,
  kClockXbarOutLpoClk = 3U,
  kClockXbarOutMcgIrClk = 4U,
  kClockXbarOutOsc32kSel = 5U,
  kClockXbarOutOsc0erClk = 6U,
  kClockXbarOutMcgPllClk = 7U
}
 SIM XBAR clock out source select, SIM_CTRL_REG.
 
enum  clock_pllfll_sel_t {
  kClockPllFllSelFll,
  kClockPllFllSelPll,
  kClockPllFllSelFll,
  kClockPllFllSelPll,
  kClockPllFllSelFll,
  kClockPllFllSelPll,
  kClockPllFllSelFll,
  kClockPllFllSelPll,
  kClockPllFllSelFll = 0U,
  kClockPllFllSelPll = 1U,
  kClockPllFllSelBus = 2U,
  kClockPllFllSelOsc32k = 3U
}
 SIM PLLFLLSEL clock source select, SIM_CTRL_REG.
 
enum  sim_spi_out_invert_sel_t {
  kSimSpiOutInvertSel0,
  kSimSpiOutInvertSel1
}
 SIM SPI output signal inverting setting, SIM_CTRL_REG.
 
enum  sim_sadc_trg_clk_sel_t {
  kSimSAdcTrgClksel0,
  kSimSAdcTrgClksel1,
  kSimSAdcTrgClksel2,
  kSimSAdcTrgClksel3
}
 SIM SAR ADC trigger clock select, SIM_CTRL_REG.
 
enum  sim_lptmr_src_sel_t {
  kSimLptmrSrcSel0,
  kSimLptmrSrcSel1,
  kSimLptmrSrcSel2
}
 SIM LP timer channel x source selection, SIM_SOPT1_CFG.
 
enum  sim_vref_buff_input_sel_t {
  kSimVrefBuffInputSel0,
  kSimVrefBuffInputSel1
}
 SIM VrefBuffer input selection, SIM_MISC_CTL.
 
enum  sim_tmr_Primary_src_sel_t {
  kSimTmrPrimarySrcSel0,
  kSimTmrPrimarySrcSel1,
  kSimTmrPrimarySrcSel2,
  kSimTmrPrimarySrcDisable
}
 SIM Quadtimer channel x primary count source selection, SIM_MISC_CTL.
 
enum  sim_tmr_sencond_src_sel_t {
  kSimTmrSecondSrcSel0,
  kSimTmrSecondSrcSel1
}
 SIM Quadtimer channel x secondary count source selection.
 
enum  clock_tmr0_pll_src_t {
  kSimTmr0PllClkSel0,
  kSimTmr0PllClkSel1
}
 SIM Timer channel 0 PLL clock selection, SIM_MISC_CTL.
 
enum  sim_ewm_input_sel_t {
  kSimEwmInputSel0,
  kSimEwmInputSel1
}
 SIM External watchdog monitor input selection, SIM_MISC_CTL.
 
enum  sim_uart_irda_sel_t {
  kSimUartIrdaSel0,
  kSimUartIrdaSel1
}
 SIM UARTx IRDA selection, SIM_MISC_CTL.
 
enum  sim_uart_irda_type_sel_t {
  kSimUartIrdaTypeSelA,
  kSimUartIrdaTypeSelB
}
 SIM UARTx IRDA modulation type selection, SIM_MISC_CTL.
 
enum  sim_afe_clk_pad_dir_t {
  kSimAfeClkPadDirInput,
  kSimAfeClkPadDirOutput
}
 SIM, Controls the direction of the AFE CLK pin, SIM_MISC_CTL.
 
enum  sim_dma_done_sel_t {
  kSimDmaDoneSel0,
  kSimDmaDoneSel1,
  kSimDmaDoneSel2,
  kSimDmaDoneSel3
}
 SIM DMA done selection, SIM_MISC_CTL.
 
enum  sim_adc_trg_src_sel_t {
  kSimAdcTrgSelXbar,
  kSimAdcTrgSelPdb
}
 SIM ADC trigger source selection, SIM_MISC_CTL.
 
enum  sim_clock_gate_name_t {
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
  kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
  kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
  kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U),
  kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
  kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
  kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
  kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
  kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U),
  kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
  kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
  kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
  kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
  kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U),
  kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
  kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U),
  kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
  kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U),
  kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U),
  kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U),
  kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 7U),
  kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 8U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U),
  kSimClockGateUart3 = FSL_SIM_SCGC_BIT(4U, 13U),
  kSimClockGateVref0 = FSL_SIM_SCGC_BIT(4U, 15U),
  kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 18U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 21U),
  kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 22U),
  kSimClockGateSlcd0 = FSL_SIM_SCGC_BIT(5U, 3U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 6U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 7U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 8U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortF = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortG = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortH = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGatePortI = FSL_SIM_SCGC_BIT(5U, 14U),
  kSimClockGateIRtc0 = FSL_SIM_SCGC_BIT(5U, 16U),
  kSimClockGateIRtcRegFile0 = FSL_SIM_SCGC_BIT(5U, 17U),
  kSimClockGateXbar0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateQuadTmr0 = FSL_SIM_SCGC_BIT(5U, 23U),
  kSimClockGateQuadTmr1 = FSL_SIM_SCGC_BIT(5U, 24U),
  kSimClockGateQuadTmr2 = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateQuadTmr3 = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateRnga0 = FSL_SIM_SCGC_BIT(6U, 9U),
  kSimClockGateLpuart0 = FSL_SIM_SCGC_BIT(6U, 10U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 11U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 13U),
  kSimClockGatePit1 = FSL_SIM_SCGC_BIT(6U, 14U),
  kSimClockGateAfe0 = FSL_SIM_SCGC_BIT(6U, 16U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 20U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePortJ = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGatePortK = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGatePortL = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGatePortM = FSL_SIM_SCGC_BIT(6U, 26U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(6U, 28U),
  kSimClockGateMpu0 = FSL_SIM_SCGC_BIT(7U, 0U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 1U),
  kSimClockGateCau0 = FSL_SIM_SCGC_BIT(7U, 2U),
  kSimClockGateMmau0 = FSL_SIM_SCGC_BIT(7U, 3U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U),
  kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U),
  kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U),
  kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
  kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U),
  kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
  kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U),
  kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U),
  kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U),
  kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
  kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U),
  kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
  kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U),
  kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U),
  kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U),
  kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
  kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U),
  kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
  kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U),
  kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U),
  kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U),
  kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
  kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U),
  kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
  kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U),
  kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U),
  kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U),
  kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U),
  kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U),
  kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U),
  kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U),
  kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U),
  kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U),
  kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U),
  kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U),
  kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U),
  kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U),
  kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U),
  kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U),
  kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U),
  kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U),
  kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U),
  kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U),
  kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U),
  kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U),
  kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U),
  kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U),
  kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U),
  kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U),
  kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U),
  kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U),
  kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U),
  kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U),
  kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U),
  kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U),
  kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U),
  kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U),
  kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U),
  kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U)
}
 

Functions

IP related clock feature APIs
static void SIM_HAL_EnableClock (SIM_Type *base, sim_clock_gate_name_t name)
 Enable the clock for specific module. More...
 
static void SIM_HAL_DisableClock (SIM_Type *base, sim_clock_gate_name_t name)
 Disable the clock for specific module. More...
 
static bool SIM_HAL_GetGateCmd (SIM_Type *base, sim_clock_gate_name_t name)
 Get the the clock gate state for specific module. More...
 
static uint32_t SIM_HAL_GetSRamSize (SIM_Type *base)
 Gets the Kinetis system RAM size in the System Options register 1(SIM_SOPT1). More...
 
static void CLOCK_HAL_SetExternalRefClock32kSrc (SIM_Type *base, clock_er32k_src_t setting)
 Set the clock selection of ERCLK32K. More...
 
static clock_er32k_src_t CLOCK_HAL_GetExternalRefClock32kSrc (SIM_Type *base)
 Get the clock selection of ERCLK32K. More...
 
static void SIM_HAL_SetRamBitlinePrechargeCmd (SIM_Type *base, bool enable)
 Sets the RAM Bitline Precharge enable setting. More...
 
static bool SIM_HAL_GetRamBitlinePrechargeCmd (SIM_Type *base)
 Gets the RAM Bitline Precharge enable setting. More...
 
static void SIM_HAL_SetRamSrcBiasCmd (SIM_Type *base, bool disable)
 Sets the source bias of SRAM arrays enable setting. More...
 
static bool SIM_HAL_GetRamSrcBiasCmd (SIM_Type *base)
 Gets the source bias of SRAM arrays enable setting. More...
 
void SIM_HAL_SetLptmrChSelMode (SIM_Type *base, uint8_t channel, sim_lptmr_src_sel_t select)
 Sets the LPTMR channel x source select setting. More...
 
sim_lptmr_src_sel_t SIM_HAL_GetLptmrChSelMode (SIM_Type *base, uint8_t channel)
 Gets the LPTMR channel x source select setting. More...
 
static void CLOCK_HAL_SetClkOutSel (SIM_Type *base, clock_clkout_src_t setting)
 Set CLKOUTSEL selection. More...
 
static clock_clkout_src_t CLOCK_HAL_GetClkOutSel (SIM_Type *base)
 Get CLKOUTSEL selection. More...
 
static void CLOCK_HAL_SetSAdcTrgClkSel (SIM_Type *base, sim_sadc_trg_clk_sel_t setting)
 Set SAR ADC trigger clock selection. More...
 
static sim_sadc_trg_clk_sel_t CLOCK_HAL_GetSAdcTrgClkSel (SIM_Type *base)
 Get the SAR ADC trigger clock selection. More...
 
static void CLOCK_HAL_SetTmrCntFreezeCmd (SIM_Type *base, sim_tmr_cnt_freeze_sel_t setting)
 Set TMR counter freeze setting. More...
 
static sim_tmr_cnt_freeze_sel_t CLOCK_HAL_GetTmrCntFreezeCmd (SIM_Type *base)
 Get the TMR counter freeze setting. More...
 
static void CLOCK_HAL_SetLpuartClkSel (SIM_Type *base, clock_lpuart_src_t setting)
 Set LPUART clock source selection. More...
 
static clock_lpuart_src_t CLOCK_HAL_GetLpuartClkSel (SIM_Type *base)
 Get the LPUART clock source selection. More...
 
static void CLOCK_HAL_SetAfeOutDivCmd (SIM_Type *base, sim_afe_clk_div_sel_t setting)
 Set AFE output clock dividing setting. More...
 
static sim_afe_clk_div_sel_t CLOCK_HAL_GetAfeOutDivCmd (SIM_Type *base)
 Get the AFE output clock dividing setting. More...
 
static void CLOCK_HAL_SetXbarOutSel (SIM_Type *base, clock_xbar_out_src_t setting)
 Set XBARCLKOUT selection. More...
 
static clock_xbar_out_src_t CLOCK_HAL_GetXbarOutSel (SIM_Type *base)
 Get XBARCLKOUT selection. More...
 
static void CLOCK_HAL_SetPllfllSel (SIM_Type *base, clock_pllfll_sel_t setting)
 Set PLL/FLL clock selection. More...
 
static clock_pllfll_sel_t CLOCK_HAL_GetPllfllSel (SIM_Type *base)
 Get PLL/FLL clock selection. More...
 
void CLOCK_HAL_SetSpiOutInvCmd (SIM_Type *base, uint32_t instance, uint8_t inv_type, sim_spi_out_invert_sel_t setting)
 Set SPI output signal inverting setting. More...
 
sim_spi_out_invert_sel_t CLOCK_HAL_GetSpiOutInvCmd (SIM_Type *base, uint32_t instance, uint8_t inv_type)
 Get the SPI output signal inverting setting. More...
 
static void SIM_HAL_SetPllInVlpCmd (SIM_Type *base, bool enable)
 Sets the PLL VLP enable setting. More...
 
static bool SIM_HAL_GetPllInVlpCmd (SIM_Type *base)
 Gets the PLL VLP enable setting. More...
 
static void SIM_HAL_SetNmiDisCmd (SIM_Type *base, bool disable)
 Sets the NMI feature enable setting. More...
 
static bool SIM_HAL_GetNmiDisCmd (SIM_Type *base)
 Gets the NMI feature enable setting. More...
 
static uint32_t SIM_HAL_GetFamilyId (SIM_Type *base)
 Gets the Kinetis Family ID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetSubFamilyId (SIM_Type *base)
 Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetSeriesId (SIM_Type *base)
 Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetAttributeId (SIM_Type *base)
 Gets the Attribute ID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetSRamSizeId (SIM_Type *base)
 Gets the SRAM SIZE in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetRevId (SIM_Type *base)
 Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetDieId (SIM_Type *base)
 Gets the Kinetis Die ID in the System Device ID register (SIM_SDID). More...
 
static uint32_t SIM_HAL_GetPinCntId (SIM_Type *base)
 Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID). More...
 
static void CLOCK_HAL_SetSysDiv (SIM_Type *base, uint8_t setting)
 Set system clock divider. More...
 
static uint8_t CLOCK_HAL_GetSysDiv (SIM_Type *base)
 Get SYSDIV. More...
 
static void CLOCK_HAL_SetBusDiv (SIM_Type *base, uint8_t setting)
 Set BUS clock divider. More...
 
static uint8_t CLOCK_HAL_GetBusDiv (SIM_Type *base)
 Get BUS clock divider value. More...
 
static void CLOCK_HAL_SetFlashClkMode (SIM_Type *base, uint8_t setting)
 Set FLASH clock mode. More...
 
static uint8_t CLOCK_HAL_GetFlashClkMode (SIM_Type *base)
 Get FLASH clock mode value. More...
 
void CLOCK_HAL_SetOutDiv (SIM_Type *base, uint8_t sysDiv, uint8_t busDiv, uint8_t flashclkmode)
 Set all clock out dividers setting at one time. More...
 
void CLOCK_HAL_GetOutDiv (SIM_Type *base, uint8_t *sysDiv, uint8_t *busDiv, uint8_t *flashclkmode)
 Get all clock out dividers setting at one time. More...
 
static uint32_t SIM_HAL_GetProgramFlashSize (SIM_Type *base)
 Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG). More...
 
static void SIM_HAL_SetFlashDoze (SIM_Type *base, uint32_t setting)
 Sets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). More...
 
static uint32_t SIM_HAL_GetFlashDoze (SIM_Type *base)
 Gets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). More...
 
static void SIM_HAL_SetFlashDisableCmd (SIM_Type *base, bool disable)
 Sets the Flash disable setting. More...
 
static bool SIM_HAL_GetRamSize (SIM_Type *base)
 Gets the RAM size. More...
 
static bool SIM_HAL_GetFlashDisableCmd (SIM_Type *base)
 Gets the Flash disable setting. More...
 
static uint32_t SIM_HAL_GetFlashMaxAddrBlock0 (SIM_Type *base)
 Gets the Flash maximum address block in the Flash Configuration Register 2(SIM_FCFG2). More...
 
static void SIM_HAL_SetVrefBuffPowerDownCmd (SIM_Type *base, bool enable)
 Sets the VrefBuffer enable setting. More...
 
static bool SIM_HAL_GetVrefBuffPowerDownCmd (SIM_Type *base)
 Gets the VrefBuffer enable setting. More...
 
static void CLOCK_HAL_SetVrefBuffInputSel (SIM_Type *base, sim_vref_buff_input_sel_t setting)
 Set the VrefBuffer input selection. More...
 
static sim_vref_buff_input_sel_t CLOCK_HAL_GetVrefBuffInputSel (SIM_Type *base)
 Get the VrefBuffer input selection. More...
 
static void SIM_HAL_SetVrefBuffOutCmd (SIM_Type *base, bool enable)
 Sets the VrefBuffer Output enable setting. More...
 
static bool SIM_HAL_GetVrefBuffOutCmd (SIM_Type *base)
 Gets the VrefBuffer Output enable setting. More...
 
static void CLOCK_HAL_SetRtcClkSel (SIM_Type *base, clock_rtcout_src_t setting)
 Set the RTC clock source selection for RTC operation. More...
 
static clock_rtcout_src_t CLOCK_HAL_GetRtcClkSel (SIM_Type *base)
 Get the RTC clock source selection for RTC operation. More...
 
void SIM_HAL_SetTmrPrimaryCntSrcSelMode (SIM_Type *base, uint8_t channel, sim_tmr_Primary_src_sel_t select)
 Sets the Quadtimer channel x Primary Count source select setting. More...
 
sim_tmr_Primary_src_sel_t SIM_HAL_GetTmrPrimaryCntSrcSelMode (SIM_Type *base, uint8_t channel)
 Gets the Quadtimer channel x Primary Count source select setting. More...
 
void SIM_HAL_SetTmrSecondCntSrcSelMode (SIM_Type *base, uint8_t channel, sim_tmr_sencond_src_sel_t select)
 Sets the Quadtimer channel x Secondary Count source select setting. More...
 
sim_tmr_sencond_src_sel_t SIM_HAL_GetTmrSecondCntSrcSelMode (SIM_Type *base, uint8_t channel)
 Gets the Quadtimer channel x Secondary Count source select setting. More...
 
static void SIM_HAL_SetTmr0PllClkSelMode (SIM_Type *base, clock_tmr0_pll_src_t select)
 Sets the Timer0 CH0 PLL clock source select setting. More...
 
static clock_tmr0_pll_src_t SIM_HAL_GetTmr0PllClkSelMode (SIM_Type *base)
 Gets the Timer0 CH0 PLL clock source select setting. More...
 
static void SIM_HAL_SetEwmInputSelMode (SIM_Type *base, sim_ewm_input_sel_t select)
 Sets the EWM input select setting. More...
 
static sim_ewm_input_sel_t SIM_HAL_GetEwmInputSelMode (SIM_Type *base)
 Gets the EWM input select setting. More...
 
void SIM_HAL_SetUartIrdaSelMode (SIM_Type *base, uint32_t instance, sim_uart_irda_sel_t select)
 Sets the UART x IRDA select setting. More...
 
sim_uart_irda_sel_t SIM_HAL_GetUartIrdaSelMode (SIM_Type *base, uint32_t instance)
 Gets the UART x IRDA select setting. More...
 
static void SIM_HAL_SetUartModTypeSelMode (SIM_Type *base, sim_uart_irda_type_sel_t select)
 Sets the UART modulation select setting. More...
 
static sim_uart_irda_type_sel_t SIM_HAL_GetUartModTypeSelMode (SIM_Type *base)
 Gets the UART modulation select setting. More...
 
static void SIM_HAL_SetAfeClkPadDirCmd (SIM_Type *base, sim_afe_clk_pad_dir_t setting)
 Sets the AFE clock Pad direction setting. More...
 
static sim_afe_clk_pad_dir_t SIM_HAL_GetAfeClkPadDirCmd (SIM_Type *base)
 Gets the AFE clock Pad direction setting. More...
 
static void CLOCK_HAL_SetAfeClkSrc (SIM_Type *base, clock_afe_src_t select)
 Set the clock selection of AFECLKSEL. More...
 
static clock_afe_src_t CLOCK_HAL_GetAfeClkSrc (SIM_Type *base)
 Get the clock source selection of AFECLKSEL. More...
 
static void SIM_HAL_SetDmaDoneSelMode (SIM_Type *base, sim_dma_done_sel_t select)
 Sets the DMA Done select setting. More...
 
static sim_dma_done_sel_t SIM_HAL_GetDmaDoneSelMode (SIM_Type *base)
 Gets the DMA Done select setting. More...
 
static void SIM_HAL_SetAdcTrgSelMode (SIM_Type *base, sim_adc_trg_src_sel_t select)
 Sets the ADC trigger source setting. More...
 
static sim_adc_trg_src_sel_t SIM_HAL_GetAdcTrgSelMode (SIM_Type *base)
 Gets the ADC trigger source setting. More...
 
static bool SIM_HAL_GetRtcOscStatusCmd (SIM_Type *base)
 Gets the status of RTC oscillator. More...
 
uint16_t SIM_HAL_GetAdcCompensationValueCmd (SIM_Type *base, uint8_t temperature)
 Gets the ADC Temperature Compensation Value. More...