CADC Peripheral Driver

Overview

This section describes the programming interface of the CADC Peripheral driver. The CADC peripheral driver configures the Cyclic ADC (12-bit Cyclic Analog-to-Digital Converter). It handles initialization, configuration and controlling the conversion of this module.

CADC Driver model building

CADC driver has four objects:

• ADC Converter - CADC module has two ADC converters, ConvA and ConvB, which are the two independent sample and hold (S/H) circuits. They can work simultaneously or individually for each conversion. The driver provides APIs to configure each converter separately.
  • Conversion sequence - Conversion sequence is the basic execution unit for the CADC module. Starting a single conversion either launches a sequence of conversions or a scan. Each slot in the sequence can be configured as an input sample channel from the channel multiplexer, The conversion result is stored in the related result register. Additional features, such as zero-crossing detection and low/high limit detection can be attached to the conversion for each slot. The driver provides APIs to configure each slot in the sequence.
  • Input multiplexer - 16 input single-end inputs for the CADC module are grouped for each converter, ANA0 - ANA7 belong to ConvA, ANB0 - ANB7 belong to ConvB. As a result, only the unique host converter can convert the indicated input channel. Inputs are grouped for the differential sample so that ANA[0:1], ANA[2:3], ANA[4:5], ANA[6:7], ANB[0:1], ANB[2:3], ANB[4:5], ANB[6:7]. In this case, a channel with an even number is positive and the channel with an odd number is negative. The driver provides APIs to configure each input channel.
  • Global setting - Global setting covers all shared configurations. The driver provides APIs to configure the global setting.

CADC Work mode

The ADC operates either in a sequential scan mode or a parallel scan mode. In the sequential scan mode, the scan sequence is determined by defining the 16 sample slots that are processed in order, SAMPLE[0:15]. In the parallel scan mode, ConvA processes SAMPLE[0:7] in order and ConvB processes SAMPLE[8:15] in order.

• In the sequential scan mode, a scan takes up to 16 single-ended or differential samples, one at a time.
• In the parallel scan mode, 8 of the 16 samples are allocated to ConvA and the other 8 are allocated to ConvB. Two converters operate in parallel such that each can take at most 8 samples. ConvA can sample only analog inputs ANA[0:7] and ConvB can sample only analog inputs ANB[0:7].

The parallel scan mode is simultaneous or non-simultaneous:

• In the simultaneous scan mode, parallel scans in the two converters occur simultaneously and result in simultaneous pairs of conversions, one by ConvA and one by ConvB. The two converters share the same start, stop, sync, end-of-scan interrupt enable control, and interrupts. Scanning in both converters terminates when either converter encounters a disabled sample.
• In the non-simultaneous scan mode, parallel scans in the two converters occur independently. Each converter has its own start, stop, sync, end-of-scan interrupt enable controls, and interrupts. Scanning in either converter terminates only when that converter encounters a disabled sample.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform the scan sequence repeatedly until manually stopped. The single scan (once mode) differs from the triggered mode only in that SYNC input signals must be re-armed after each use and subsequent SYNC inputs are ignored until the SYNC input is re-armed. Arming can occur any time after the SYNC pulse, including while the scan is still in process.

CADC Interrupt

There are three categories of ADC interrupts:

• Threshold interrupts, which are caused by three different events:
  • Zero crossing — occurs if the current result value has a sign change from the previous result.
  • Low limit exceeded error — occurs when the current result value is less than the setting value for the low limit. The raw result value is compared to the setting value for the low limit before the offset register value is subtracted.
  • High limit exceeded error — is asserted if the current result value is greater than the setting value for the high limit. The raw result value is compared to the setting value for the high limit.
• Conversion complete interrupts, which are generated upon completion of any scan and convert sequence when enabling the interrupt.
• Scan interrupts are generated when a sample is converted. This allows processing of intermediate conversion data during a scan.

CADC Call diagram

When using the CADC module, all four objects should be configured according to the application requirements. This example illustrates how to use the CADC driver.

// Four kinds of structures to configure Cyclic ADC with conversion sequence. //
cadc_controller_config_t g_AdcUserConfigStruct;
cadc_chn_config_t g_AdcChnConfigStruct;
cadc_converter_config_t g_AdcConvConfigStruct;
cadc_slot_config_t g_AdcSlotConfigStruct;

static uint32_t CADC_DRV_TEST_PollingMode(uint32_t instance);

int main(void)
{
    uint32_t idx;
    uint32_t errCounter = 0U;
    uint32_t totalErrCounter = 0U;

    hardware_init();
    dbg_uart_init();

    PRINTF("\r\nCADC PD driver Test: Start...\r\n");

    for (idx = 0U; idx < 1; idx++)
    {
        printf("CADC instance: %d.\r\n", idx);
        errCounter = 0U;

        errCounter += CADC_DRV_TEST_PollingMode(idx);

        PRINTF("CADC %d PD driver Test error counter: %d\r\n", idx, errCounter);
        totalErrCounter += errCounter;
    }

    PRINTF("CADC PD driver Test: End\r\n");

    // Print log for auto run detection. //
    PRINTF("CADC PD driver Test ");
    if (0U == totalErrCounter)
    {
        PRINTF("Succeed\r\n");
    }
    else
    {
        PRINTF("Error\r\n");
    }

    while ('c' != getchar()) {}
    return 0;
}

static uint32_t CADC_DRV_TEST_PollingMode(uint32_t instance)
{
    volatile int tmp;
    g_CurADCInstance = instance;

    CADC_DRV_StructInitUserConfigDefault(&g_AdcUserConfigStruct);
    CADC_DRV_Init(instance, &g_AdcUserConfigStruct);

    // Configure ADC sample input channel. //
    g_AdcChnConfigStruct.diffChns = kCAdcDiffChnANA4_5;
    g_AdcChnConfigStruct.diffSelMode = kCAdcChnSelBoth;
    g_AdcChnConfigStruct.gainMode = kCAdcSGainBy1;
    CADC_DRV_ConfigSampleChn(instance, &g_AdcChnConfigStruct);

    g_AdcChnConfigStruct.diffChns = kCAdcDiffChnANA6_7;
    g_AdcChnConfigStruct.diffSelMode = kCAdcChnSelBoth;
    g_AdcChnConfigStruct.gainMode = kCAdcSGainBy1;
    CADC_DRV_ConfigSampleChn(instance, &g_AdcChnConfigStruct);

    g_AdcChnConfigStruct.diffChns = kCAdcDiffChnANB4_5;
    g_AdcChnConfigStruct.diffSelMode = kCAdcChnSelBoth;
    g_AdcChnConfigStruct.gainMode = kCAdcSGainBy1;
    CADC_DRV_ConfigSampleChn(instance, &g_AdcChnConfigStruct);

    g_AdcChnConfigStruct.diffChns = kCAdcDiffChnANB6_7;
    g_AdcChnConfigStruct.diffSelMode = kCAdcChnSelBoth;
    g_AdcChnConfigStruct.gainMode = kCAdcSGainBy1;
    CADC_DRV_ConfigSampleChn(instance, &g_AdcChnConfigStruct);

    // Configure ADC converters. //
    g_AdcConvConfigStruct.dmaEnable = false;
    g_AdcConvConfigStruct.stopEnable = false; // Ungate the converter. //
    g_AdcConvConfigStruct.syncEnable = false; // Software trigger only. //
    g_AdcConvConfigStruct.endOfScanIntEnable = false; // No interrupt. //
    g_AdcConvConfigStruct.clkDivValue = 0x4U;
    g_AdcConvConfigStruct.useChnInputAsVrefH = false;
    g_AdcConvConfigStruct.useChnInputAsVrefL = false;
    g_AdcConvConfigStruct.speedMode = kCAdcConvClkLimitBy25MHz;
    g_AdcConvConfigStruct.sampleWindowCount = 0U; 
    CADC_DRV_ConfigConverter(instance, kCAdcConvA, &g_AdcConvConfigStruct);
    CADC_DRV_ConfigConverter(instance, kCAdcConvB, &g_AdcConvConfigStruct);
    while (CADC_DRV_GetConvFlag(instance, kCAdcConvA, kCAdcConvPowerDown) ) {}
    while (CADC_DRV_GetConvFlag(instance, kCAdcConvB, kCAdcConvPowerDown) ) {}


    // Configure slot in conversion sequence. //
    // Common setting. //
    g_AdcSlotConfigStruct.zeroCrossingMode = kCAdcZeroCrossingDisable;
    g_AdcSlotConfigStruct.lowLimitValue = 0U;
    g_AdcSlotConfigStruct.highLimitValue = 0xFFFU;
    g_AdcSlotConfigStruct.offsetValue = 0U;
    g_AdcSlotConfigStruct.syncPointEnable = false;
    g_AdcSlotConfigStruct.syncIntEnable = false;
    // For each slot in conversion sequence. //
    // Slot 0. //
    g_AdcSlotConfigStruct.diffChns = kCAdcDiffChnANA4_5;
    g_AdcSlotConfigStruct.diffSel = kCAdcChnSelBoth;
    g_AdcSlotConfigStruct.slotDisable = false;
    CADC_DRV_ConfigSeqSlot(instance, 0U, &g_AdcSlotConfigStruct);
    // Slot 1. //
    g_AdcSlotConfigStruct.diffChns = kCAdcDiffChnANA6_7;
    g_AdcSlotConfigStruct.diffSel = kCAdcChnSelBoth;
    g_AdcSlotConfigStruct.slotDisable = false;
    CADC_DRV_ConfigSeqSlot(instance, 1U, &g_AdcSlotConfigStruct);
    // Slot 2. //
    g_AdcSlotConfigStruct.diffChns = kCAdcDiffChnANB4_5;
    g_AdcSlotConfigStruct.diffSel = kCAdcChnSelBoth;
    g_AdcSlotConfigStruct.slotDisable = false;
    CADC_DRV_ConfigSeqSlot(instance, 2U, &g_AdcSlotConfigStruct);
    // Slot 3. //
    g_AdcSlotConfigStruct.diffChns = kCAdcDiffChnANB6_7;
    g_AdcSlotConfigStruct.diffSel = kCAdcChnSelBoth;
    g_AdcSlotConfigStruct.slotDisable = false;
    CADC_DRV_ConfigSeqSlot(instance, 3U, &g_AdcSlotConfigStruct);

    g_AdcSlotConfigStruct.slotDisable = true;
    CADC_DRV_ConfigSeqSlot(instance, 4U, &g_AdcSlotConfigStruct);

    //
      Trigger the conversion sequence.
      When in sequential simult mode, operate converter A will driver the
      main conversion sequence. 
    //
    CADC_DRV_SoftTriggerConv(instance, kCAdcConvA);

    // Wait the data to be ready. //
    while (!CADC_DRV_GetSlotFlag(instance, 1U << 0U, kCAdcSlotReady)) { }
    while (!CADC_DRV_GetSlotFlag(instance, 1U << 1U, kCAdcSlotReady)) { }
    while (!CADC_DRV_GetSlotFlag(instance, 1U << 2U, kCAdcSlotReady)) { }
    while (!CADC_DRV_GetSlotFlag(instance, 1U << 3U, kCAdcSlotReady)) { }

    tmp = (int16_t)CADC_DRV_GetSeqSlotConvValue(instance, 0U);
    PRINTF("ADC Slot %2d value: %d\r\n", 0U, tmp);
    tmp = (int16_t)CADC_DRV_GetSeqSlotConvValue(instance, 1U);
    PRINTF("ADC Slot %2d value: %d\r\n", 1U, tmp);
    tmp = (int16_t)CADC_DRV_GetSeqSlotConvValue(instance, 2U);
    PRINTF("ADC Slot %2d value: %d\r\n", 2U, tmp);
    tmp = (int16_t)CADC_DRV_GetSeqSlotConvValue(instance, 3U);
    PRINTF("ADC Slot %2d value: %d\r\n", 3U, tmp);

    CADC_DRV_Deinit(instance);
    return 0U;
}

Enumerations
enum	cadc_conv_id_t {   kCAdcConvA = 0U,   kCAdcConvB = 1U }
	Defines the type of enumerating ADC converter ID. More...
enum	cadc_flag_t {   kCAdcConvInProgress = 0U,   kCAdcConvEndOfScanInt = 1U,   kCAdcConvPowerDown = 2U,   kCAdcZeroCrossingInt = 3U,   kCAdcLowLimitInt = 4U,   kCAdcHighLimitInt = 5U,   kCAdcSlotReady = 6U,   kCAdcSlotLowLimitEvent = 7U,   kCAdcSlotHighLimitEvent = 8U,   kCAdcSlotCrossingEvent = 9U }
	Defines types for an enumerating event. More...

Variables
ADC_Type *	g_cadcBaseAddr []
	Table of base addresses for ADC instances. More...
IRQn_Type	g_cadcErrIrqId [ADC_INSTANCE_COUNT]
	Table to save ADC IRQ enumeration numbers defined in the CMSIS header file. More...

CADC Driver
cadc_status_t	CADC_DRV_StructInitUserConfigDefault (cadc_controller_config_t *userConfigPtr)
	Populates the user configuration structure for the CyclicADC common settings. More...
cadc_status_t	CADC_DRV_Init (uint32_t instance, const cadc_controller_config_t *userConfigPtr)
	Initializes the CyclicADC module for a global configuration. More...
cadc_status_t	CADC_DRV_Deinit (uint32_t instance)
	De-initializes the CyclicADC module. More...
cadc_status_t	CADC_DRV_StructInitConvConfigDefault (cadc_converter_config_t *configPtr)
	Populates the user configuration structure for each converter. More...
cadc_status_t	CADC_DRV_ConfigConverter (uint32_t instance, cadc_conv_id_t convId, const cadc_converter_config_t *configPtr)
	Configures each converter in the CyclicADC module. More...
cadc_status_t	CADC_DRV_ConfigSampleChn (uint32_t instance, const cadc_chn_config_t *configPtr)
	Configures the input channel for ADC conversion. More...
cadc_status_t	CADC_DRV_ConfigSeqSlot (uint32_t instance, uint32_t slotIdx, const cadc_slot_config_t *configPtr)
	Configures each slot for the ADC conversion sequence. More...
void	CADC_DRV_SoftTriggerConv (uint32_t instance, cadc_conv_id_t convId)
	Triggers the ADC conversion sequence by software. More...
uint16_t	CADC_DRV_GetSeqSlotConvValue (uint32_t instance, uint32_t slotIdx)
	Reads the conversion value and returns an absolute value. More...
bool	CADC_DRV_GetFlag (uint32_t instance, cadc_flag_t flag)
	Gets the global event flag. More...
void	CADC_DRV_ClearFlag (uint32_t instance, cadc_flag_t flag)
	Clears the global event flag. More...
bool	CADC_DRV_GetConvFlag (uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag)
	Gets the flag for each converter event. More...
void	CADC_DRV_ClearConvFlag (uint32_t instance, cadc_conv_id_t convId, cadc_flag_t flag)
	Clears the flag for each converter event. More...
uint16_t	CADC_DRV_GetSlotFlag (uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag)
	Gets the flag for each slot event. More...
void	CADC_DRV_ClearSlotFlag (uint32_t instance, uint16_t slotIdxMask, cadc_flag_t flag)
	Clears the flag for each slot event. More...

Enumeration Type Documentation

enum cadc_conv_id_t

Enumerator
kCAdcConvA	ID for ADC converter A.
kCAdcConvB	ID for ADC converter B.

enum cadc_flag_t

Enumerator
kCAdcConvInProgress	Conversion in progress for each converter.
kCAdcConvEndOfScanInt	End of scan interrupt.
kCAdcConvPowerDown	The converter is powered Down.
kCAdcZeroCrossingInt	Zero crossing interrupt.
kCAdcLowLimitInt	Low limit interrupt.
kCAdcHighLimitInt	High limit interrupt.
kCAdcSlotReady	Sample is ready to be read.
kCAdcSlotLowLimitEvent	Low limit event for each slot.
kCAdcSlotHighLimitEvent	High limit event for each slot.
kCAdcSlotCrossingEvent	Zero crossing event for each slot.

Function Documentation

cadc_status_t CADC_DRV_StructInitUserConfigDefault

(

cadc_controller_config_t *

userConfigPtr

)

This function populates the cadc_user_config_t structure with default settings, which are used in polling mode for ADC conversion. These settings are:

.zeroCrossingIntEnable = false; .lowLimitIntEnable = false; .highLimitIntEnable = false; .scanMode = kCAdcScanOnceSequential; .parallelSimultModeEnable = false; .dmaSrc = kCAdcDmaTriggeredByEndOfScan; .autoStandbyEnable = false; .powerUpDelayCount = 0x2AU; .autoPowerDownEnable = false;

Parameters

userConfigPtr

Pointer to structure of "cadc_controller_config_t".

Returns

Execution status.

cadc_status_t CADC_DRV_Init	(	uint32_t	instance,
		const cadc_controller_config_t *	userConfigPtr
	)

This function configures the CyclicADC module for the global configuration which is shared by all converters.

Parameters

instance	Instance ID number.
userConfigPtr	Pointer to structure of "cadc_controller_config_t".

Returns

Execution status.

cadc_status_t CADC_DRV_Deinit

(

uint32_t

instance

)

This function shuts down the CyclicADC module and disables related IRQs.

Parameters

instance

Instance ID number.

Returns

Execution status.

cadc_status_t CADC_DRV_StructInitConvConfigDefault

(

cadc_converter_config_t *

configPtr

)

This function populates the cadc_conv_config_t structure with default settings, which are used in polling mode for ADC conversion. These settings are:

.dmaEnable = false; .stopEnable = false; .syncEnable = false; .endOfScanIntEnable = false; .clkDivValue = 0x3FU; .useChnInputAsVrefH = false; .useChnInputAsVrefL = false; .speedMode = kCAdcConvClkLimitBy25MHz; .sampleWindowCount = 0U;

Parameters

configPtr

Pointer to structure of "cadc_converter_config_t".

Returns

Execution status.

cadc_status_t CADC_DRV_ConfigConverter	(	uint32_t	instance,
		cadc_conv_id_t	convId,
		const cadc_converter_config_t *	configPtr
	)

This function configures each converter in the CyclicADC module. However, when the multiple converters are operating simultaneously, the converter settings are interrelated. For more information, see the appropriate device reference manual.

Parameters

instance	Instance ID number.
convId	Converter ID. See "cadc_conv_id_t".
configPtr	Pointer to configure structure. See "cadc_converter_config_t".

Returns

Execution status.

cadc_status_t CADC_DRV_ConfigSampleChn	(	uint32_t	instance,
		const cadc_chn_config_t *	configPtr
	)

This function configures the input channel for ADC conversion. The CyclicADC module input channels are organized in pairs. The configuration can be set for each channel in the pair.

Parameters

instance	Instance ID number.
configPtr	Pointer to configure structure. See "cadc_chn_config_t".

Returns

Execution status.

cadc_status_t CADC_DRV_ConfigSeqSlot	(	uint32_t	instance,
		uint32_t	slotIdx,
		const cadc_slot_config_t *	configPtr
	)

This function configures each slot in the ADC conversion sequence. ADC conversion sequence is the basic execution unit in the CyclicADC module. However, the sequence should be configured slot-by-slot. The end of the sequence is a slot that is configured as disabled.

Parameters

instance	Instance ID number.
slotIdx	Indicated slot number, available in range of 0 - 15.
configPtr	Pointer to configure structure. See "cadc_slot_config_t".

Returns

Execution status.

void CADC_DRV_SoftTriggerConv	(	uint32_t	instance,
		cadc_conv_id_t	convId
	)

This function triggers the ADC conversion by executing a software command. It starts the conversion if no other SYNC input (hardware trigger) is needed.

Parameters

instance	Instance ID number.
convId	Indicated converter. See "cadc_conv_id_t".

uint16_t CADC_DRV_GetSeqSlotConvValue	(	uint32_t	instance,
		uint32_t	slotIdx
	)

This function reads the conversion value from each slot in a conversion sequence. The return value is the absolute value without being signed.

Parameters

instance	Instance ID number.
slotIdx	Indicated slot number, available in range of 0 - 15.

Returns

The conversion value.

bool CADC_DRV_GetFlag	(	uint32_t	instance,
		cadc_flag_t	flag
	)

This function gets the global flag of the CyclicADC module.

Parameters

instance	Instance ID number.
flag	Indicated event. See "cadc_flag_t".

Returns

Assertion of indicated event.

void CADC_DRV_ClearFlag	(	uint32_t	instance,
		cadc_flag_t	flag
	)

This function clears the global event flag of the CyclicADC module.

Parameters

instance	Instance ID number.
flag	Indicated event. See "cadc_flag_t".

bool CADC_DRV_GetConvFlag	(	uint32_t	instance,
		cadc_conv_id_t	convId,
		cadc_flag_t	flag
	)

This function gets the flag for each converter event.

Parameters

instance	Instance ID number.
convId	Indicated converter.
flag	Indicated event. See "cadc_flag_t".

Returns

Assertion of indicated event.

void CADC_DRV_ClearConvFlag	(	uint32_t	instance,
		cadc_conv_id_t	convId,
		cadc_flag_t	flag
	)

This function clears the flag for each converter event.

Parameters

instance	Instance ID number.
convId	Indicated converter.
flag	Indicated event. See "cadc_flag_t".

uint16_t CADC_DRV_GetSlotFlag	(	uint32_t	instance,
		uint16_t	slotIdxMask,
		cadc_flag_t	flag
	)

This function gets the flag for each slot event in the conversion in sequence.

Parameters

instance	Instance ID number.
slotIdxMask	Indicated slot number's mask.
flag	Indicated event. See "cadc_flag_t".

Returns

Assertion of indicated event.

void CADC_DRV_ClearSlotFlag	(	uint32_t	instance,
		uint16_t	slotIdxMask,
		cadc_flag_t	flag
	)

This function clears the flag for each slot event in the conversion in sequence.

Parameters

instance	Instance ID number.
slotIdxMask	Indicated slot number's mask.
flag	Indicated event. See "cadc_flag_t".

Variable Documentation

ADC_Type* g_cadcBaseAddr[]

IRQn_Type g_cadcErrIrqId[ADC_INSTANCE_COUNT]