Kinetis SDK v.1.3 API Reference Manual
Rev. 0
Freescale Semiconductor, Inc.
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This section describes the programming interface of the DMA HAL driver.
Data Structures | |
struct | dma_channel_link_config_t |
Data structure for data structure configuration. More... | |
struct | dma_error_status_t |
Data structure to get status of the DMA channel status. More... | |
Enumerations | |
enum | dma_status_t { , kStatus_DMA_InvalidArgument = 1U, kStatus_DMA_Fail = 2U } |
DMA status. More... | |
enum | dma_transfer_size_t { kDmaTransfersize32bits = 0x0U, kDmaTransfersize8bits = 0x1U, kDmaTransfersize16bits = 0x2U } |
DMA transfer size type. More... | |
enum | dma_modulo_t |
Configuration type for the DMA modulo. | |
enum | dma_channel_link_type_t { kDmaChannelLinkDisable = 0x0U, kDmaChannelLinkChan1AndChan2 = 0x1U, kDmaChannelLinkChan1 = 0x2U, kDmaChannelLinkChan1AfterBCR0 = 0x3U } |
DMA channel link type. More... | |
enum | dma_transfer_type_t { kDmaPeripheralToMemory, kDmaMemoryToPeripheral, kDmaMemoryToMemory, kDmaPeripheralToPeripheral } |
Type for DMA transfer. More... | |
DMA HAL channel configuration | |
void | DMA_HAL_Init (DMA_Type *base, uint32_t channel) |
Sets all registers of the channel to 0. More... | |
void | DMA_HAL_ConfigTransfer (DMA_Type *base, uint32_t channel, dma_transfer_size_t size, dma_transfer_type_t type, uint32_t sourceAddr, uint32_t destAddr, uint32_t length) |
Basic DMA transfer configuration. More... | |
static void | DMA_HAL_SetSourceAddr (DMA_Type *base, uint32_t channel, uint32_t address) |
Configures the source address. More... | |
static void | DMA_HAL_SetDestAddr (DMA_Type *base, uint32_t channel, uint32_t address) |
Configures the source address. More... | |
static void | DMA_HAL_SetTransferCount (DMA_Type *base, uint32_t channel, uint32_t count) |
Configures the bytes to be transferred. More... | |
static uint32_t | DMA_HAL_GetUnfinishedByte (DMA_Type *base, uint32_t channel) |
Gets the left bytes not to be transferred. More... | |
static void | DMA_HAL_SetIntCmd (DMA_Type *base, uint8_t channel, bool enable) |
Enables the interrupt for the DMA channel after the work is done. More... | |
static void | DMA_HAL_SetCycleStealCmd (DMA_Type *base, uint8_t channel, bool enable) |
Configures the DMA transfer mode to cycle steal or continuous modes. More... | |
static void | DMA_HAL_SetAutoAlignCmd (DMA_Type *base, uint8_t channel, bool enable) |
Configures the auto-align feature. More... | |
static void | DMA_HAL_SetAsyncDmaRequestCmd (DMA_Type *base, uint8_t channel, bool enable) |
Configures the a-sync DMA request feature. More... | |
static void | DMA_HAL_SetSourceIncrementCmd (DMA_Type *base, uint32_t channel, bool enable) |
Enables/disables the source increment. More... | |
static void | DMA_HAL_SetDestIncrementCmd (DMA_Type *base, uint32_t channel, bool enable) |
Enables/disables destination increment. More... | |
static void | DMA_HAL_SetSourceTransferSize (DMA_Type *base, uint32_t channel, dma_transfer_size_t transfersize) |
Configures the source transfer size. More... | |
static void | DMA_HAL_SetDestTransferSize (DMA_Type *base, uint32_t channel, dma_transfer_size_t transfersize) |
Configures the destination transfer size. More... | |
static void | DMA_HAL_SetTriggerStartCmd (DMA_Type *base, uint32_t channel, bool enable) |
Triggers the start. More... | |
static void | DMA_HAL_SetSourceModulo (DMA_Type *base, uint32_t channel, dma_modulo_t modulo) |
Configures the modulo for the source address. More... | |
static void | DMA_HAL_SetDestModulo (DMA_Type *base, uint32_t channel, dma_modulo_t modulo) |
Configures the modulo for the destination address. More... | |
static void | DMA_HAL_SetDmaRequestCmd (DMA_Type *base, uint32_t channel, bool enable) |
Enables/disables the DMA request. More... | |
static void | DMA_HAL_SetDisableRequestAfterDoneCmd (DMA_Type *base, uint32_t channel, bool enable) |
Configures the DMA request state after the work is done. More... | |
void | DMA_HAL_SetChanLink (DMA_Type *base, uint8_t channel, dma_channel_link_config_t *mode) |
Configures the channel link feature. More... | |
static void | DMA_HAL_ClearStatus (DMA_Type *base, uint8_t channel) |
Clears the status of the DMA channel. More... | |
dma_error_status_t | DMA_HAL_GetStatus (DMA_Type *base, uint8_t channel) |
Gets the DMA controller channel status. More... | |
struct dma_channel_link_config_t |
Data Fields | |
dma_channel_link_type_t | linkType |
Channel link type. | |
uint32_t | channel1 |
Channel 1 configuration. | |
uint32_t | channel2 |
Channel 2 configuration. | |
struct dma_error_status_t |
Data Fields | |
uint32_t | dmaBytesToBeTransffered |
Bytes to be transferred. | |
bool | dmaTransDone |
DMA channel transfer is done. More... | |
bool | dmaBusy |
DMA is running. More... | |
bool | dmaPendingRequest |
A transfer remains. More... | |
bool | dmaDestBusError |
Bus error on destination address. | |
bool | dmaSourceBusError |
Bus error on source address. | |
bool | dmaConfigError |
Configuration error. | |
bool dma_error_status_t::dmaTransDone |
bool dma_error_status_t::dmaBusy |
bool dma_error_status_t::dmaPendingRequest |
enum dma_status_t |
enum dma_transfer_size_t |
enum dma_transfer_type_t |
void DMA_HAL_Init | ( | DMA_Type * | base, |
uint32_t | channel | ||
) |
base | DMA base. |
channel | DMA channel. |
void DMA_HAL_ConfigTransfer | ( | DMA_Type * | base, |
uint32_t | channel, | ||
dma_transfer_size_t | size, | ||
dma_transfer_type_t | type, | ||
uint32_t | sourceAddr, | ||
uint32_t | destAddr, | ||
uint32_t | length | ||
) |
base | DMA base. |
channel | DMA channel. |
size | Size to be transferred on each DMA write/read. Source/Dest share the same write/read size. |
type | Transfer type. |
sourceAddr | Source address. |
destAddr | Destination address. |
length | Bytes to be transferred. |
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inlinestatic |
Each SAR contains the byte address used by the DMA to read data. The SARn is typically aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. Bits 31-20 of this register must be written with one of the only four allowed values. Each of these allowed values corresponds to a valid region of the devices' memory map. The allowed values are: 0x000x_xxxx 0x1FFx_xxxx 0x200x_xxxx 0x400x_xxxx After they are written with one of the allowed values, bits 31-20 read back as the written value. After they are written with any other value, bits 31-20 read back as an indeterminate value.
This function enables the request for a specified channel.
base | DMA base. |
channel | DMA channel. |
address | memory address pointing to the source address. |
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inlinestatic |
Each DAR contains the byte address used by the DMA to read data. The DARn is typically aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. Bits 31-20 of this register must be written with one of the only four allowed values. Each of these allowed values corresponds to a valid region of the devices' memory map. The allowed values are: 0x000x_xxxx 0x1FFx_xxxx 0x200x_xxxx 0x400x_xxxx After they are written with one of the allowed values, bits 31-20 read back as the written value. After they are written with any other value, bits 31-20 read back as an indeterminate value.
This function enables the request for specified channel.
base | DMA base. |
channel | DMA channel. |
address | Destination address. |
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inlinestatic |
Transfer bytes must be written with a value equal to or less than 0F_FFFFh. After being written with a value in this range, bits 23-20 of the BCR read back as 1110b. A write to the BCR with a value greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After they are written with a value in this range, bits 23-20 of BCR read back as 1111b.
base | DMA base. |
channel | DMA channel. |
count | bytes to be transferred. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
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inlinestatic |
This function enables the request for specified channel.
base | DMA base. |
channel | DMA channel. |
enable | True means enable interrupt, false means disable. |
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inlinestatic |
If continuous mode is enabled, DMA continuously makes write/read transfers until BCR decrement to 0. If continuous mode is disabled, DMA write/read is only triggered on every request. s
base | DMA base. |
channel | DMA channel. |
enable | 1 means cycle-steal mode, 0 means continuous mode. |
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inlinestatic |
If auto-align is enabled, the appropriate address register increments, regardless of whether it is a source increment or a destination increment.
base | DMA base. |
channel | DMA channel. |
enable | 0 means disable auto-align. 1 means enable auto-align. |
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inlinestatic |
Enables/disables the a-synchronization mode in a STOP mode for each DMA channel.
base | DMA base. |
channel | DMA channel. |
enable | 0 means disable DMA request a-sync. 1 means enable DMA request -. |
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inlinestatic |
Controls whether the source address increments after each successful transfer. If enabled, the SAR increments by 1,2,4 as determined by the transfer size.
base | DMA base. |
channel | DMA channel. |
enable | Enabled/Disable increment. |
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inlinestatic |
Controls whether the destination address increments after each successful transfer. If enabled, the DAR increments by 1,2,4 as determined by the transfer size.
base | DMA base. |
channel | DMA channel. |
enable | Enabled/Disable increment. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
transfersize | enum type for transfer size. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
transfersize | enum type for transfer size. |
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inlinestatic |
When the DMA begins the transfer, the START bit is cleared automatically after one module clock and always reads as logic 0.
base | DMA base. |
channel | DMA channel. |
enable | Enable/disable trigger start. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
modulo | enum data type for source modulo. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
modulo | enum data type for dest modulo. |
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inlinestatic |
base | DMA base. |
channel | DMA channel. |
enable | Enable/disable dma request. |
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inlinestatic |
Disables/enables the DMA request after a DMA DONE is generated. If it works in the loop mode, this bit should not be set.
base | DMA base address. |
channel | DMA channel. |
enable | 0 means DMA request would not be disabled after work done. 1 means disable. |
void DMA_HAL_SetChanLink | ( | DMA_Type * | base, |
uint8_t | channel, | ||
dma_channel_link_config_t * | mode | ||
) |
base | DMA base address. |
channel | DMA channel. |
mode | Mode of channel link in DMA. |
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inlinestatic |
This function clears the status for a specified DMA channel. The error status and done status are cleared.
base | DMA base address. |
channel | DMA channel. |
dma_error_status_t DMA_HAL_GetStatus | ( | DMA_Type * | base, |
uint8_t | channel | ||
) |
Gets the status of the DMA channel. The user can get the error status, as to whether the descriptor is finished or there are bytes left.
base | DMA base address. |
channel | DMA channel. |