The KSDK provides a peripheral driver for the Synchronous DRAM Controller block of Kinetis devices.
The SDRAM controller commands include the initialize MRS command, precharge command, enter/exit self-refresh command, and enable/disable auto-refresh command. Use the SDRAMC_SendCommand() to send these commands to SDRAM to initialize it. The SDRAMC_EnableWriteProtect() is provided to enable/disable the write protection. The SDRAMC_EnableOperateValid() is provided to enable/disable the operation valid.
Typical use case
This example shows how to use the SDRAM Controller driver to initialize the external 16 bit port-size 8-column SDRAM chip. Initialize the SDRAM controller and run the initialization sequence. The external SDRAM is initialized and the SDRAM read and write is available.
First, initialize the SDRAM Controller.
uint32_t clockSrc;
{
15625,
clockSrc,
};
{
SDRAM_START_ADDRESS,
0x7c0000,
};
Then, run the initialization sequence.
(uint8_t *)(SDRAM_START_ADDRESS) = SDRAM_COMMAND_ACCESSVALUE;
delay;
addr = ....;
mrsAddr = (uint8_t *)(SDRAM_START_ADDRESS + addr);
mrsAddr = SDRAM_COMMAND_ACCESSVALUE;
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enum | sdramc_refresh_time_t {
kSDRAMC_RefreshThreeClocks = 0x0U,
kSDRAMC_RefreshSixClocks,
kSDRAMC_RefreshNineClocks
} |
| SDRAM controller auto-refresh timing. More...
|
|
enum | sdramc_latency_t {
kSDRAMC_LatencyZero = 0x0U,
kSDRAMC_LatencyOne,
kSDRAMC_LatencyTwo,
kSDRAMC_LatencyThree
} |
| Setting latency for SDRAM controller timing specifications. More...
|
|
enum | sdramc_command_bit_location_t {
kSDRAMC_Commandbit17 = 0x0U,
kSDRAMC_Commandbit18,
kSDRAMC_Commandbit19,
kSDRAMC_Commandbit20,
kSDRAMC_Commandbit21,
kSDRAMC_Commandbit22,
kSDRAMC_Commandbit23,
kSDRAMC_Commandbit24
} |
| SDRAM controller command bit location. More...
|
|
enum | sdramc_command_t {
kSDRAMC_ImrsCommand = 0x0U,
kSDRAMC_PrechargeCommand,
kSDRAMC_SelfrefreshEnterCommand,
kSDRAMC_SelfrefreshExitCommand,
kSDRAMC_AutoRefreshEnableCommand,
kSDRAMC_AutoRefreshDisableCommand
} |
| SDRAM controller command. More...
|
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enum | sdramc_port_size_t {
kSDRAMC_PortSize32Bit = 0x0U,
kSDRAMC_PortSize8Bit,
kSDRAMC_PortSize16Bit
} |
| SDRAM port size. More...
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enum | sdramc_block_selection_t {
kSDRAMC_Block0 = 0x0U,
kSDRAMC_Block1
} |
| SDRAM controller block selection. More...
|
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struct sdramc_blockctl_config_t |
uint32_t sdramc_blockctl_config_t::address |
uint32_t sdramc_blockctl_config_t::addressMask |
struct sdramc_refresh_config_t |
uint32_t sdramc_refresh_config_t::sdramRefreshRow |
uint32_t sdramc_refresh_config_t::busClock_Hz |
Defines a configure structure and uses the SDRAMC_Configure() function to make necessary initializations.
If both SDRAM blocks are used, use the two continuous blockConfig.
uint8_t sdramc_config_t::numBlockConfig |
Enumerator |
---|
kSDRAMC_RefreshThreeClocks |
The refresh timing with three bus clocks.
|
kSDRAMC_RefreshSixClocks |
The refresh timing with six bus clocks.
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kSDRAMC_RefreshNineClocks |
The refresh timing with nine bus clocks.
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The latency setting will affects the following SDRAM timing specifications:
- trcd: SRAS assertion to SCAS assertion
- tcasl: SCAS assertion to data out
- tras: ACTV command to Precharge command
- trp: Precharge command to ACTV command
- trwl, trdl: Last data input to Precharge command
- tep: Last data out to Precharge command
the details of the latency setting and timing specifications are shown on the following table list:
latency trcd: tcasl tras trp trwl,trdl tep
0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock
1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock
2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock
3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock
Enumerator |
---|
kSDRAMC_LatencyZero |
Latency 0.
|
kSDRAMC_LatencyOne |
Latency 1.
|
kSDRAMC_LatencyTwo |
Latency 2.
|
kSDRAMC_LatencyThree |
Latency 3.
|
Enumerator |
---|
kSDRAMC_Commandbit17 |
Command bit location is bit 17.
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kSDRAMC_Commandbit18 |
Command bit location is bit 18.
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kSDRAMC_Commandbit19 |
Command bit location is bit 19.
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kSDRAMC_Commandbit20 |
Command bit location is bit 20.
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kSDRAMC_Commandbit21 |
Command bit location is bit 21.
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kSDRAMC_Commandbit22 |
Command bit location is bit 22.
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kSDRAMC_Commandbit23 |
Command bit location is bit 23.
|
kSDRAMC_Commandbit24 |
Command bit location is bit 24.
|
Enumerator |
---|
kSDRAMC_ImrsCommand |
Initiate MRS command.
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kSDRAMC_PrechargeCommand |
Initiate precharge command.
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kSDRAMC_SelfrefreshEnterCommand |
Enter self-refresh command.
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kSDRAMC_SelfrefreshExitCommand |
Exit self-refresh command.
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kSDRAMC_AutoRefreshEnableCommand |
Enable Auto refresh command.
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kSDRAMC_AutoRefreshDisableCommand |
Disable Auto refresh command.
|
Enumerator |
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kSDRAMC_PortSize32Bit |
32-Bit port size.
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kSDRAMC_PortSize8Bit |
8-Bit port size.
|
kSDRAMC_PortSize16Bit |
16-Bit port size.
|
Enumerator |
---|
kSDRAMC_Block0 |
Select SDRAM block 0.
|
kSDRAMC_Block1 |
Select SDRAM block 1.
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This function ungates the SDRAM controller clock and initializes the SDRAM controller. This function must be called before calling any other SDRAM controller driver functions. Example
refreshConfig.busClock = 60000000;
blockConfig.
address = SDRAM_START_ADDRESS;
config.totalBlocks = 1;
- Parameters
-
base | SDRAM controller peripheral base address. |
configure | The SDRAM configuration structure pointer. |
void SDRAMC_Deinit |
( |
SDRAM_Type * |
base | ) |
|
This function gates the SDRAM controller clock. As a result, the SDRAM controller module doesn't work after calling this function.
- Parameters
-
base | SDRAM controller peripheral base address. |
This function sends the command to SDRAM. There are precharge command, initialize MRS command, auto-refresh enable/disable command, and self-refresh enter/exit commands. Note the self-refresh enter/exit commands are all blocks setting and "block" are ignored. Ensure to set the right "block" when send other commands.
- Parameters
-
base | SDRAM controller peripheral base address. |
block | The block selection. |
command | The SDRAM command, see "sdramc_command_t". kSDRAMC_ImrsCommand - Initialize MRS command
kSDRAMC_PrechargeCommand - Initialize precharge command
kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command
kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command
kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command
kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command |
- Returns
- Command execution status. All commands except the "initialize MRS command" and "precharge command" return kStatus_Success directly. For "initialize MRS command" and "precharge command" return kStatus_Success when the command success else return kStatus_Fail.
- Parameters
-
base | SDRAM peripheral base address. |
block | The block which is selected. |
enable | True enable write protection, false disable write protection. |
- Parameters
-
base | SDRAM peripheral base address. |
block | The block which is selected. |
enable | True enable the operation valid, false disable the operation valid. |