The MCUXpresso SDK provides APIs for MCUXpresso SDK devices' clock operation.
Get frequency
A centralized function CLOCK_GetFreq gets different clock type frequencies by passing a clock name. For example, pass a kCLOCK_CoreSysClk to get the core clock and pass a kCLOCK_BusClk to get the bus clock. Additionally, there are separate functions to get the frequency. For example, use CLOCK_GetCoreSysClkFreq to get the core clock frequency and CLOCK_GetBusClkFreq to get the bus clock frequency. Using these functions reduces the image size.
External clock frequency
The external clocks EXTAL0/EXTAL1/EXTAL32 are decided by the board level design. The Clock driver uses variables g_xtal0Freq/g_xtal1Freq/g_xtal32Freq to save clock frequencies. Likewise, the APIs CLOCK_SetXtal0Freq, CLOCK_SetXtal1Freq, and CLOCK_SetXtal32Freq are used to set these variables.
The upper layer must set these values correctly. For example, after OSC0(SYSOSC) is initialized using CLOCK_InitOsc0 or CLOCK_InitSysOsc, the upper layer should call the CLOCK_SetXtal0Freq. Otherwise, the clock frequency get functions may not receive valid values. This is useful for multicore platforms where only one core calls CLOCK_InitOsc0 to initialize OSC0 and other cores call CLOCK_SetXtal0Freq.
|
| enum | clock_name_t {
kCLOCK_CoreSysClk,
kCLOCK_PlatClk,
kCLOCK_BusClk,
kCLOCK_FlexBusClk,
kCLOCK_FlashClk,
kCLOCK_FastPeriphClk,
kCLOCK_PllFllSelClk,
kCLOCK_Er32kClk,
kCLOCK_Osc0ErClk,
kCLOCK_Osc1ErClk,
kCLOCK_Osc0ErClkUndiv,
kCLOCK_McgFixedFreqClk,
kCLOCK_McgInternalRefClk,
kCLOCK_McgFllClk,
kCLOCK_McgPll0Clk,
kCLOCK_McgPll1Clk,
kCLOCK_McgExtPllClk,
kCLOCK_McgPeriphClk,
kCLOCK_McgIrc48MClk,
kCLOCK_LpoClk
} |
| | Clock name used to get clock frequency. More...
|
| |
| enum | clock_usb_src_t {
kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U),
kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U),
kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U)
} |
| | USB clock source definition. More...
|
| |
| enum | clock_ip_name_t |
| | Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. More...
|
| |
| enum | osc_mode_t {
kOSC_ModeExt = 0U,
kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK,
kOSC_ModeOscHighGain
} |
| | OSC work mode. More...
|
| |
| enum | _osc_cap_load {
kOSC_Cap2P = OSC_CR_SC2P_MASK,
kOSC_Cap4P = OSC_CR_SC4P_MASK,
kOSC_Cap8P = OSC_CR_SC8P_MASK,
kOSC_Cap16P = OSC_CR_SC16P_MASK
} |
| | Oscillator capacitor load setting. More...
|
| |
| enum | _oscer_enable_mode {
kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK,
kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK
} |
| | OSCERCLK enable mode. More...
|
| |
| enum | mcg_fll_src_t {
kMCG_FllSrcExternal,
kMCG_FllSrcInternal
} |
| | MCG FLL reference clock source select. More...
|
| |
| enum | mcg_irc_mode_t {
kMCG_IrcSlow,
kMCG_IrcFast
} |
| | MCG internal reference clock select. More...
|
| |
| enum | mcg_dmx32_t {
kMCG_Dmx32Default,
kMCG_Dmx32Fine
} |
| | MCG DCO Maximum Frequency with 32.768 kHz Reference. More...
|
| |
| enum | mcg_drs_t {
kMCG_DrsLow,
kMCG_DrsMid,
kMCG_DrsMidHigh,
kMCG_DrsHigh
} |
| | MCG DCO range select. More...
|
| |
| enum | mcg_pll_ref_src_t {
kMCG_PllRefOsc0,
kMCG_PllRefOsc1
} |
| | MCG PLL reference clock select. More...
|
| |
| enum | mcg_clkout_src_t {
kMCG_ClkOutSrcOut,
kMCG_ClkOutSrcInternal,
kMCG_ClkOutSrcExternal
} |
| | MCGOUT clock source. More...
|
| |
| enum | mcg_atm_select_t {
kMCG_AtmSel32k,
kMCG_AtmSel4m
} |
| | MCG Automatic Trim Machine Select. More...
|
| |
| enum | mcg_oscsel_t {
kMCG_OscselOsc,
kMCG_OscselRtc,
kMCG_OscselIrc
} |
| | MCG OSC Clock Select. More...
|
| |
| enum | mcg_pll_clk_select_t { kMCG_PllClkSelPll0
} |
| | MCG PLLCS select. More...
|
| |
| enum | mcg_monitor_mode_t {
kMCG_MonitorNone,
kMCG_MonitorInt,
kMCG_MonitorReset
} |
| | MCG clock monitor mode. More...
|
| |
| enum | _mcg_status {
kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0),
kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1),
kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2),
kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3),
kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4),
kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5),
kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)
} |
| | MCG status. More...
|
| |
| enum | _mcg_status_flags_t {
kMCG_Osc0LostFlag = (1U << 0U),
kMCG_Osc0InitFlag = (1U << 1U),
kMCG_RtcOscLostFlag = (1U << 4U),
kMCG_Pll0LostFlag = (1U << 5U),
kMCG_Pll0LockFlag = (1U << 6U)
} |
| | MCG status flags. More...
|
| |
| enum | _mcg_irclk_enable_mode {
kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK,
kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK
} |
| | MCG internal reference clock (MCGIRCLK) enable mode definition. More...
|
| |
| enum | _mcg_pll_enable_mode {
kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK,
kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK
} |
| | MCG PLL clock enable mode definition. More...
|
| |
| enum | mcg_mode_t {
kMCG_ModeFEI = 0U,
kMCG_ModeFBI,
kMCG_ModeBLPI,
kMCG_ModeFEE,
kMCG_ModeFBE,
kMCG_ModeBLPE,
kMCG_ModePBE,
kMCG_ModePEE,
kMCG_ModeError
} |
| | MCG mode definitions. More...
|
| |
|
| mcg_mode_t | CLOCK_GetMode (void) |
| | Gets the current MCG mode. More...
|
| |
| status_t | CLOCK_SetFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FEI mode. More...
|
| |
| status_t | CLOCK_SetFeeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FEE mode. More...
|
| |
| status_t | CLOCK_SetFbiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FBI mode. More...
|
| |
| status_t | CLOCK_SetFbeMode (uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FBE mode. More...
|
| |
| status_t | CLOCK_SetBlpiMode (void) |
| | Sets the MCG to BLPI mode. More...
|
| |
| status_t | CLOCK_SetBlpeMode (void) |
| | Sets the MCG to BLPE mode. More...
|
| |
| status_t | CLOCK_SetPbeMode (mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
| | Sets the MCG to PBE mode. More...
|
| |
| status_t | CLOCK_SetPeeMode (void) |
| | Sets the MCG to PEE mode. More...
|
| |
| status_t | CLOCK_ExternalModeToFbeModeQuick (void) |
| | Switches the MCG to FBE mode from the external mode. More...
|
| |
| status_t | CLOCK_InternalModeToFbiModeQuick (void) |
| | Switches the MCG to FBI mode from internal modes. More...
|
| |
| status_t | CLOCK_BootToFeiMode (mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FEI mode during system boot up. More...
|
| |
| status_t | CLOCK_BootToFeeMode (mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void(*fllStableDelay)(void)) |
| | Sets the MCG to FEE mode during system bootup. More...
|
| |
| status_t | CLOCK_BootToBlpiMode (uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) |
| | Sets the MCG to BLPI mode during system boot up. More...
|
| |
| status_t | CLOCK_BootToBlpeMode (mcg_oscsel_t oscsel) |
| | Sets the MCG to BLPE mode during sytem boot up. More...
|
| |
| status_t | CLOCK_BootToPeeMode (mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) |
| | Sets the MCG to PEE mode during system boot up. More...
|
| |
| status_t | CLOCK_SetMcgConfig (mcg_config_t const *config) |
| | Sets the MCG to a target mode. More...
|
| |
| struct sim_clock_config_t |
| uint8_t sim_clock_config_t::pllFllSel |
| uint8_t sim_clock_config_t::er32kSrc |
| uint32_t sim_clock_config_t::clkdiv1 |
| uint8_t oscer_config_t::enableMode |
| uint8_t oscer_config_t::erclkDiv |
Defines the configuration data structure to initialize the OSC. When porting to a new board, set the following members according to the board setting:
- freq: The external frequency.
- workMode: The OSC module mode.
| uint32_t osc_config_t::freq |
| uint8_t osc_config_t::capLoad |
| uint8_t mcg_pll_config_t::enableMode |
| uint8_t mcg_pll_config_t::prdiv |
| uint8_t mcg_pll_config_t::vdiv |
When porting to a new board, set the following members according to the board setting:
- frdiv: If the FLL uses the external reference clock, set this value to ensure that the external reference clock divided by frdiv is in the 31.25 kHz to 39.0625 kHz range.
- The PLL reference clock divider PRDIV: PLL reference clock frequency after PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to FSL_FEATURE_MCG_PLL_REF_MAX range.
| uint8_t mcg_config_t::irclkEnableMode |
| uint8_t mcg_config_t::fcrdiv |
| uint8_t mcg_config_t::frdiv |
| #define MCG_CONFIG_CHECK_PARAM 0U |
Some MCG settings must be changed with conditions, for example:
- MCGIRCLK settings, such as the source, divider, and the trim value should not change when MCGIRCLK is used as a system clock source.
- MCG_C7[OSCSEL] should not be changed when the external reference clock is used as a system clock source. For example, in FBE/BLPE/PBE modes.
- The users should only switch between the supported clock modes.
MCG functions check the parameter and MCG status before setting, if not allowed to change, the functions return error. The parameter checking increases code size, if code size is a critical requirement, change MCG_CONFIG_CHECK_PARAM to 0 to disable parameter checking.
| #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 |
When set to 0, peripheral drivers will enable clock in initialize function and disable clock in de-initialize function. When set to 1, peripheral driver will not control the clock, application could contol the clock out of the driver.
- Note
- All drivers share this feature switcher. If it is set to 1, application should handle clock enable and disable for all drivers.
| #define MCG_INTERNAL_IRC_48M 48000000U |
Value:{ \
kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
}
Value:{ \
kCLOCK_Spi0, kCLOCK_Spi1 \
}
Value:{ \
kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
}
Value:{ \
kCLOCK_Dac0, kCLOCK_Dac1 \
}
Value:{ \
kCLOCK_Adc0, kCLOCK_Adc1 \
}
Value:{ \
kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
}
Value:{ \
kCLOCK_I2c0, kCLOCK_I2c1 \
}
Value:{ \
kCLOCK_Cmp0, kCLOCK_Cmp1 \
}
| Enumerator |
|---|
| kCLOCK_CoreSysClk |
Core/system clock.
|
| kCLOCK_PlatClk |
Platform clock.
|
| kCLOCK_BusClk |
Bus clock.
|
| kCLOCK_FlexBusClk |
FlexBus clock.
|
| kCLOCK_FlashClk |
Flash clock.
|
| kCLOCK_FastPeriphClk |
Fast peripheral clock.
|
| kCLOCK_PllFllSelClk |
The clock after SIM[PLLFLLSEL].
|
| kCLOCK_Er32kClk |
External reference 32K clock (ERCLK32K)
|
| kCLOCK_Osc0ErClk |
OSC0 external reference clock (OSC0ERCLK)
|
| kCLOCK_Osc1ErClk |
OSC1 external reference clock (OSC1ERCLK)
|
| kCLOCK_Osc0ErClkUndiv |
OSC0 external reference undivided clock(OSC0ERCLK_UNDIV).
|
| kCLOCK_McgFixedFreqClk |
MCG fixed frequency clock (MCGFFCLK)
|
| kCLOCK_McgInternalRefClk |
MCG internal reference clock (MCGIRCLK)
|
| kCLOCK_McgFllClk |
MCGFLLCLK.
|
| kCLOCK_McgPll0Clk |
MCGPLL0CLK.
|
| kCLOCK_McgPll1Clk |
MCGPLL1CLK.
|
| kCLOCK_McgExtPllClk |
EXT_PLLCLK.
|
| kCLOCK_McgPeriphClk |
MCG peripheral clock (MCGPCLK)
|
| kCLOCK_McgIrc48MClk |
MCG IRC48M clock.
|
| kCLOCK_LpoClk |
LPO clock.
|
| Enumerator |
|---|
| kCLOCK_UsbSrcPll0 |
Use PLL0.
|
| kCLOCK_UsbSrcIrc48M |
Use IRC48M.
|
| kCLOCK_UsbSrcExt |
Use USB_CLKIN.
|
| Enumerator |
|---|
| kOSC_ModeExt |
Use an external clock.
|
| kOSC_ModeOscLowPower |
Oscillator low power.
|
| kOSC_ModeOscHighGain |
Oscillator high gain.
|
| Enumerator |
|---|
| kOSC_Cap2P |
2 pF capacitor load
|
| kOSC_Cap4P |
4 pF capacitor load
|
| kOSC_Cap8P |
8 pF capacitor load
|
| kOSC_Cap16P |
16 pF capacitor load
|
| Enumerator |
|---|
| kOSC_ErClkEnable |
Enable.
|
| kOSC_ErClkEnableInStop |
Enable in stop mode.
|
| Enumerator |
|---|
| kMCG_FllSrcExternal |
External reference clock is selected.
|
| kMCG_FllSrcInternal |
The slow internal reference clock is selected.
|
| Enumerator |
|---|
| kMCG_IrcSlow |
Slow internal reference clock selected.
|
| kMCG_IrcFast |
Fast internal reference clock selected.
|
| Enumerator |
|---|
| kMCG_Dmx32Default |
DCO has a default range of 25%.
|
| kMCG_Dmx32Fine |
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
|
| Enumerator |
|---|
| kMCG_DrsLow |
Low frequency range.
|
| kMCG_DrsMid |
Mid frequency range.
|
| kMCG_DrsMidHigh |
Mid-High frequency range.
|
| kMCG_DrsHigh |
High frequency range.
|
| Enumerator |
|---|
| kMCG_PllRefOsc0 |
Selects OSC0 as PLL reference clock.
|
| kMCG_PllRefOsc1 |
Selects OSC1 as PLL reference clock.
|
| Enumerator |
|---|
| kMCG_ClkOutSrcOut |
Output of the FLL is selected (reset default)
|
| kMCG_ClkOutSrcInternal |
Internal reference clock is selected.
|
| kMCG_ClkOutSrcExternal |
External reference clock is selected.
|
| Enumerator |
|---|
| kMCG_AtmSel32k |
32 kHz Internal Reference Clock selected
|
| kMCG_AtmSel4m |
4 MHz Internal Reference Clock selected
|
| Enumerator |
|---|
| kMCG_OscselOsc |
Selects System Oscillator (OSCCLK)
|
| kMCG_OscselRtc |
Selects 32 kHz RTC Oscillator.
|
| kMCG_OscselIrc |
Selects 48 MHz IRC Oscillator.
|
| Enumerator |
|---|
| kMCG_PllClkSelPll0 |
PLL0 output clock is selected.
|
| Enumerator |
|---|
| kMCG_MonitorNone |
Clock monitor is disabled.
|
| kMCG_MonitorInt |
Trigger interrupt when clock lost.
|
| kMCG_MonitorReset |
System reset when clock lost.
|
| Enumerator |
|---|
| kStatus_MCG_ModeUnreachable |
Can't switch to target mode.
|
| kStatus_MCG_ModeInvalid |
Current mode invalid for the specific function.
|
| kStatus_MCG_AtmBusClockInvalid |
Invalid bus clock for ATM.
|
| kStatus_MCG_AtmDesiredFreqInvalid |
Invalid desired frequency for ATM.
|
| kStatus_MCG_AtmIrcUsed |
IRC is used when using ATM.
|
| kStatus_MCG_AtmHardwareFail |
Hardware fail occurs during ATM.
|
| kStatus_MCG_SourceUsed |
Can't change the clock source because it is in use.
|
| Enumerator |
|---|
| kMCG_Osc0LostFlag |
OSC0 lost.
|
| kMCG_Osc0InitFlag |
OSC0 crystal initialized.
|
| kMCG_RtcOscLostFlag |
RTC OSC lost.
|
| kMCG_Pll0LostFlag |
PLL0 lost.
|
| kMCG_Pll0LockFlag |
PLL0 locked.
|
| Enumerator |
|---|
| kMCG_IrclkEnable |
MCGIRCLK enable.
|
| kMCG_IrclkEnableInStop |
MCGIRCLK enable in stop mode.
|
| Enumerator |
|---|
| kMCG_PllEnableIndependent |
MCGPLLCLK enable independent of the MCG clock mode.
Generally, the PLL is disabled in FLL modes (FEI/FBI/FEE/FBE). Setting the PLL clock enable independent, enables the PLL in the FLL modes.
|
| kMCG_PllEnableInStop |
MCGPLLCLK enable in STOP mode.
|
| Enumerator |
|---|
| kMCG_ModeFEI |
FEI - FLL Engaged Internal.
|
| kMCG_ModeFBI |
FBI - FLL Bypassed Internal.
|
| kMCG_ModeBLPI |
BLPI - Bypassed Low Power Internal.
|
| kMCG_ModeFEE |
FEE - FLL Engaged External.
|
| kMCG_ModeFBE |
FBE - FLL Bypassed External.
|
| kMCG_ModeBLPE |
BLPE - Bypassed Low Power External.
|
| kMCG_ModePBE |
PBE - PLL Bypassed External.
|
| kMCG_ModePEE |
PEE - PLL Engaged External.
|
| kMCG_ModeError |
Unknown mode.
|
| static void CLOCK_SetLpuartClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set LPUART clock source. |
| static void CLOCK_SetEr32kClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set ERCLK32K clock source. |
| static void CLOCK_SetTraceClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set debug trace clock source. |
| static void CLOCK_SetPllFllSelClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set PLLFLLSEL clock source. |
| static void CLOCK_SetClkOutClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set CLKOUT source. |
| static void CLOCK_SetRtcClkOutClock |
( |
uint32_t |
src | ) |
|
|
inlinestatic |
- Parameters
-
| src | The value to set RTC_CLKOUT source. |
- Parameters
-
| src | USB FS clock source. |
| freq | The frequency specified by src. |
- Return values
-
| true | The clock is set successfully. |
| false | The clock source is invalid to get proper USB FS clock. |
| static void CLOCK_DisableUsbfs0Clock |
( |
void |
| ) |
|
|
inlinestatic |
| static void CLOCK_SetOutDiv |
( |
uint32_t |
outdiv1, |
|
|
uint32_t |
outdiv2, |
|
|
uint32_t |
outdiv3, |
|
|
uint32_t |
outdiv4 |
|
) |
| |
|
inlinestatic |
Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
- Parameters
-
| outdiv1 | Clock 1 output divider value. |
| outdiv2 | Clock 2 output divider value. |
| outdiv3 | Clock 3 output divider value. |
| outdiv4 | Clock 4 output divider value. |
This function checks the current clock configurations and then calculates the clock frequency for a specific clock name defined in clock_name_t. The MCG must be properly configured before using this function.
- Parameters
-
| clockName | Clock names defined in clock_name_t |
- Returns
- Clock frequency value in Hertz
| uint32_t CLOCK_GetCoreSysClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetPlatClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetBusClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetFlexBusClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetFlashClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetPllFllSelClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetEr32kClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetOsc0ErClkUndivFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
| uint32_t CLOCK_GetOsc0ErClkFreq |
( |
void |
| ) |
|
- Returns
- Clock frequency in Hz.
This function sets system layer clock settings in SIM module.
- Parameters
-
| config | Pointer to the configure structure. |
| static void CLOCK_SetSimSafeDivs |
( |
void |
| ) |
|
|
inlinestatic |
The system level clocks (core clock, bus clock, flexbus clock and flash clock) must be in allowed ranges. During MCG clock mode switch, the MCG output clock changes then the system level clocks may be out of range. This function could be used before MCG mode change, to make sure system level clocks are in allowed range.
- Parameters
-
| config | Pointer to the configure structure. |
| uint32_t CLOCK_GetOutClkFreq |
( |
void |
| ) |
|
This function gets the MCG output clock frequency in Hz based on the current MCG register value.
- Returns
- The frequency of MCGOUTCLK.
| uint32_t CLOCK_GetFllFreq |
( |
void |
| ) |
|
This function gets the MCG FLL clock frequency in Hz based on the current MCG register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and disabled in low power state in other modes.
- Returns
- The frequency of MCGFLLCLK.
| uint32_t CLOCK_GetInternalRefClkFreq |
( |
void |
| ) |
|
This function gets the MCG internal reference clock frequency in Hz based on the current MCG register value.
- Returns
- The frequency of MCGIRCLK.
| uint32_t CLOCK_GetFixedFreqClkFreq |
( |
void |
| ) |
|
This function gets the MCG fixed frequency clock frequency in Hz based on the current MCG register value.
- Returns
- The frequency of MCGFFCLK.
| uint32_t CLOCK_GetPll0Freq |
( |
void |
| ) |
|
This function gets the MCG PLL0 clock frequency in Hz based on the current MCG register value.
- Returns
- The frequency of MCGPLL0CLK.
| static void CLOCK_SetLowPowerEnable |
( |
bool |
enable | ) |
|
|
inlinestatic |
Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and PBI modes, enabling low power sets the MCG to BLPI mode. When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
- Parameters
-
| enable | True to enable MCG low power, false to disable MCG low power. |
| status_t CLOCK_SetInternalRefClkConfig |
( |
uint8_t |
enableMode, |
|
|
mcg_irc_mode_t |
ircs, |
|
|
uint8_t |
fcrdiv |
|
) |
| |
This function sets the MCGIRCLK base on parameters. It also selects the IRC source. If the fast IRC is used, this function sets the fast IRC divider. This function also sets whether the MCGIRCLK is enabled in stop mode. Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, using the function in these modes it is not allowed.
- Parameters
-
| enableMode | MCGIRCLK enable mode, OR'ed value of _mcg_irclk_enable_mode. |
| ircs | MCGIRCLK clock source, choose fast or slow. |
| fcrdiv | Fast IRC divider setting (FCRDIV). |
- Return values
-
| kStatus_MCG_SourceUsed | Because the internall reference clock is used as a clock source, the confuration should not be changed. Otherwise, a glitch occurs. |
| kStatus_Success | MCGIRCLK configuration finished successfully. |
| status_t CLOCK_SetExternalRefClkConfig |
( |
mcg_oscsel_t |
oscsel | ) |
|
Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], and waits for the clock source to be stable. Because the external reference clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
- Parameters
-
| oscsel | MCG external reference clock source, MCG_C7[OSCSEL]. |
- Return values
-
| kStatus_MCG_SourceUsed | Because the external reference clock is used as a clock source, the confuration should not be changed. Otherwise, a glitch occurs. |
| kStatus_Success | External reference clock set successfully. |
| static void CLOCK_SetFllExtRefDiv |
( |
uint8_t |
frdiv | ) |
|
|
inlinestatic |
Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
- Parameters
-
| frdiv | The FLL external reference clock divider value, MCG_C1[FRDIV]. |
This function sets us the PLL0 in FLL mode and reconfigures the PLL0. Ensure that the PLL reference clock is enabled before calling this function and that the PLL0 is not used as a clock source. The function CLOCK_CalcPllDiv gets the correct PLL divider values.
- Parameters
-
| config | Pointer to the configuration structure. |
| static void CLOCK_DisablePll0 |
( |
void |
| ) |
|
|
inlinestatic |
This function disables the PLL0 in FLL mode. It should be used together with the CLOCK_EnablePll0.
| uint32_t CLOCK_CalcPllDiv |
( |
uint32_t |
refFreq, |
|
|
uint32_t |
desireFreq, |
|
|
uint8_t * |
prdiv, |
|
|
uint8_t * |
vdiv |
|
) |
| |
This function calculates the correct reference clock divider (PRDIV) and VCO divider (VDIV) to generate a desired PLL output frequency. It returns the closest frequency match with the corresponding PRDIV/VDIV returned from parameters. If a desired frequency is not valid, this function returns 0.
- Parameters
-
| refFreq | PLL reference clock frequency. |
| desireFreq | Desired PLL output frequency. |
| prdiv | PRDIV value to generate desired PLL frequency. |
| vdiv | VDIV value to generate desired PLL frequency. |
- Returns
- Closest frequency match that the PLL was able generate.
This function sets the OSC0 clock monitor mode. See mcg_monitor_mode_t for details.
- Parameters
-
This function sets the RTC OSC clock monitor mode. See mcg_monitor_mode_t for details.
- Parameters
-
This function sets the PLL0 clock monitor mode. See mcg_monitor_mode_t for details.
- Parameters
-
| uint32_t CLOCK_GetStatusFlags |
( |
void |
| ) |
|
This function gets the MCG clock status flags. All status flags are returned as a logical OR of the enumeration _mcg_status_flags_t. To check a specific flag, compare the return value with the flag.
Example:
uint32_t mcgFlags;
{
}
{
}
- Returns
- Logical OR value of the _mcg_status_flags_t.
| void CLOCK_ClearStatusFlags |
( |
uint32_t |
mask | ) |
|
This function clears the MCG clock lock lost status. The parameter is a logical OR value of the flags to clear. See _mcg_status_flags_t.
Example:
- Parameters
-
| mask | The status flags to clear. This is a logical OR of members of the enumeration _mcg_status_flags_t. |
| static void OSC_SetExtRefClkConfig |
( |
OSC_Type * |
base, |
|
|
oscer_config_t const * |
config |
|
) |
| |
|
inlinestatic |
This function configures the OSC external reference clock (OSCERCLK). This is an example to enable the OSCERCLK in normal and stop modes and also set the output divider to 1:
- Parameters
-
| base | OSC peripheral address. |
| config | Pointer to the configuration structure. |
| static void OSC_SetCapLoad |
( |
OSC_Type * |
base, |
|
|
uint8_t |
capLoad |
|
) |
| |
|
inlinestatic |
This function sets the specified capacitors configuration for the oscillator. This should be done in the early system level initialization function call based on the system configuration.
- Parameters
-
| base | OSC peripheral address. |
| capLoad | OR'ed value for the capacitor load option, see _osc_cap_load. |
Example:
This function initializes the OSC0 according to the board configuration.
- Parameters
-
| config | Pointer to the OSC0 configuration structure. |
| void CLOCK_DeinitOsc0 |
( |
void |
| ) |
|
This function deinitializes the OSC0.
| static void CLOCK_SetXtal0Freq |
( |
uint32_t |
freq | ) |
|
|
inlinestatic |
- Parameters
-
| freq | The XTAL0/EXTAL0 input clock frequency in Hz. |
| static void CLOCK_SetXtal32Freq |
( |
uint32_t |
freq | ) |
|
|
inlinestatic |
- Parameters
-
| freq | The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. |
| status_t CLOCK_TrimInternalRefClk |
( |
uint32_t |
extFreq, |
|
|
uint32_t |
desireFreq, |
|
|
uint32_t * |
actualFreq, |
|
|
mcg_atm_select_t |
atms |
|
) |
| |
This function trims the internal reference clock by using the external clock. If successful, it returns the kStatus_Success and the frequency after trimming is received in the parameter actualFreq. If an error occurs, the error code is returned.
- Parameters
-
| extFreq | External clock frequency, which should be a bus clock. |
| desireFreq | Frequency to trim to. |
| actualFreq | Actual frequency after trimming. |
| atms | Trim fast or slow internal reference clock. |
- Return values
-
| kStatus_Success | ATM success. |
| kStatus_MCG_AtmBusClockInvalid | The bus clock is not in allowed range for the ATM. |
| kStatus_MCG_AtmDesiredFreqInvalid | MCGIRCLK could not be trimmed to the desired frequency. |
| kStatus_MCG_AtmIrcUsed | Could not trim because MCGIRCLK is used as a bus clock source. |
| kStatus_MCG_AtmHardwareFail | Hardware fails while trimming. |
This function checks the MCG registers and determines the current MCG mode.
- Returns
- Current MCG mode or error code; See mcg_mode_t.
This function sets the MCG to FEI mode. If setting to FEI mode fails from the current mode, this function returns an error.
- Parameters
-
| dmx32 | DMX32 in FEI mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to ensure that the FLL is stable. Passing NULL does not cause a delay. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
- Note
- If
dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to a frequency above 32768 Hz.
| status_t CLOCK_SetFeeMode |
( |
uint8_t |
frdiv, |
|
|
mcg_dmx32_t |
dmx32, |
|
|
mcg_drs_t |
drs, |
|
|
void(*)(void) |
fllStableDelay |
|
) |
| |
This function sets the MCG to FEE mode. If setting to FEE mode fails from the current mode, this function returns an error.
- Parameters
-
| frdiv | FLL reference clock divider setting, FRDIV. |
| dmx32 | DMX32 in FEE mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to make sure FLL is stable. Passing NULL does not cause a delay. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
This function sets the MCG to FBI mode. If setting to FBI mode fails from the current mode, this function returns an error.
- Parameters
-
| dmx32 | DMX32 in FBI mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to make sure FLL is stable. If the FLL is not used in FBI mode, this parameter can be NULL. Passing NULL does not cause a delay. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
- Note
- If
dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz.
| status_t CLOCK_SetFbeMode |
( |
uint8_t |
frdiv, |
|
|
mcg_dmx32_t |
dmx32, |
|
|
mcg_drs_t |
drs, |
|
|
void(*)(void) |
fllStableDelay |
|
) |
| |
This function sets the MCG to FBE mode. If setting to FBE mode fails from the current mode, this function returns an error.
- Parameters
-
| frdiv | FLL reference clock divider setting, FRDIV. |
| dmx32 | DMX32 in FBE mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to make sure FLL is stable. If the FLL is not used in FBE mode, this parameter can be NULL. Passing NULL does not cause a delay. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
| status_t CLOCK_SetBlpiMode |
( |
void |
| ) |
|
This function sets the MCG to BLPI mode. If setting to BLPI mode fails from the current mode, this function returns an error.
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
| status_t CLOCK_SetBlpeMode |
( |
void |
| ) |
|
This function sets the MCG to BLPE mode. If setting to BLPE mode fails from the current mode, this function returns an error.
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
This function sets the MCG to PBE mode. If setting to PBE mode fails from the current mode, this function returns an error.
- Parameters
-
| pllcs | The PLL selection, PLLCS. |
| config | Pointer to the PLL configuration. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
- Note
- The parameter
pllcs selects the PLL. For platforms with only one PLL, the parameter pllcs is kept for interface compatibility.
- The parameter
config is the PLL configuration structure. On some platforms, it is possible to choose the external PLL directly, which renders the configuration structure not necessary. In this case, pass in NULL. For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
| status_t CLOCK_SetPeeMode |
( |
void |
| ) |
|
This function sets the MCG to PEE mode.
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
- Note
- This function only changes the CLKS to use the PLL/FLL output. If the PRDIV/VDIV are different than in the PBE mode, set them up in PBE mode and wait. When the clock is stable, switch to PEE mode.
| status_t CLOCK_ExternalModeToFbeModeQuick |
( |
void |
| ) |
|
This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. The external clock is used as the system clock souce and PLL is disabled. However, the FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEE mode to FEI mode:
- Return values
-
| kStatus_Success | Switched successfully. |
| kStatus_MCG_ModeInvalid | If the current mode is not an external mode, do not call this function. |
| status_t CLOCK_InternalModeToFbiModeQuick |
( |
void |
| ) |
|
This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. The MCGIRCLK is used as the system clock souce and PLL is disabled. However, FLL settings are not configured. This is a lite function with a small code size, which is useful during the mode switch. For example, to switch from PEI mode to FEE mode:
- Return values
-
| kStatus_Success | Switched successfully. |
| kStatus_MCG_ModeInvalid | If the current mode is not an internal mode, do not call this function. |
This function sets the MCG to FEI mode from the reset mode. It can also be used to set up MCG during system boot up.
- Parameters
-
| dmx32 | DMX32 in FEI mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to ensure that the FLL is stable. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
- Note
- If
dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed to frequency above 32768 Hz.
This function sets MCG to FEE mode from the reset mode. It can also be used to set up the MCG during system boot up.
- Parameters
-
| oscsel | OSC clock select, OSCSEL. |
| frdiv | FLL reference clock divider setting, FRDIV. |
| dmx32 | DMX32 in FEE mode. |
| drs | The DCO range selection. |
| fllStableDelay | Delay function to ensure that the FLL is stable. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
| status_t CLOCK_BootToBlpiMode |
( |
uint8_t |
fcrdiv, |
|
|
mcg_irc_mode_t |
ircs, |
|
|
uint8_t |
ircEnableMode |
|
) |
| |
This function sets the MCG to BLPI mode from the reset mode. It can also be used to set up the MCG during sytem boot up.
- Parameters
-
| fcrdiv | Fast IRC divider, FCRDIV. |
| ircs | The internal reference clock to select, IRCS. |
| ircEnableMode | The MCGIRCLK enable mode, OR'ed value of _mcg_irclk_enable_mode. |
- Return values
-
| kStatus_MCG_SourceUsed | Could not change MCGIRCLK setting. |
| kStatus_Success | Switched to the target mode successfully. |
This function sets the MCG to BLPE mode from the reset mode. It can also be used to set up the MCG during sytem boot up.
- Parameters
-
| oscsel | OSC clock select, MCG_C7[OSCSEL]. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
This function sets the MCG to PEE mode from reset mode. It can also be used to set up the MCG during system boot up.
- Parameters
-
| oscsel | OSC clock select, MCG_C7[OSCSEL]. |
| pllcs | The PLL selection, PLLCS. |
| config | Pointer to the PLL configuration. |
- Return values
-
| kStatus_MCG_ModeUnreachable | Could not switch to the target mode. |
| kStatus_Success | Switched to the target mode successfully. |
This function sets MCG to a target mode defined by the configuration structure. If switching to the target mode fails, this function chooses the correct path.
- Parameters
-
| config | Pointer to the target MCG mode configuration structure. |
- Returns
- Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
- Note
- If the external clock is used in the target mode, ensure that it is enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this function.
The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, if XTAL0 is 8 MHz:
This is important for the multicore platforms where only one core needs to set up the OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq to get a valid clock frequency.
The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the function CLOCK_SetXtal32Freq to set the value in the clock driver.
This is important for the multicore platforms where only one core needs to set up the clock. All other cores need to call the CLOCK_SetXtal32Freq to get a valid clock frequency.
